Curriculum Vitae

@ ByteDance 2020.07-Now

• OpenJDK support in ByteDance
• lossless compress library optimization
• Data Center Performance Optimization
  • Profiling in Data Center
  • AutoFDO/PGO
• ARM Server Complier Toolchains Support
  • ARM Server GCC-Based Cross Compiler Toolchains

@ Alibaba 2018.07-2020.07

• Coordinate software and hardware Optimization for DNN/CNN Accelerator implemented in FPGA
  • Graph Optimization/ Pipeline Optimization
  • Register Allocation /IR Optimization/Code Generation
• Wasm Compiler ：Accelerate Ant block chain smart contract in T-Head C910
  • front end , wasm to llvm IR
• ARM Compiler Toolchains Support
  • build benchmark system for Compiler optimization
  • general optimization like pgo/lto/autofdo

@ SDU-Embedded 2015.07-2018.06

• Shared Last Level Cache management and Memory Scheduling for GPGPU with hybrid Main Memory
  • Main idea : memory coalescing aware cache management
  • NVM vs DRAM trade off : energy efficient main memory scheduling
  • publish 2 papers to DATE 2017 and TECS 2018 with Ph.D Guan Wang
• Compiler Assisted Cache Coherence for GPGPUs
  • a static analysis framework for thread block and cache block index
  • software strategy to eliminate cache coherence for GPGPUs
• Energy Efficient Object Detection for Edge Computing
  • 3rd place in DAC SDC 2018 GPU category
  • News
    • in SDU https://www.view.sdu.edu.cn/info/1023/106392.htm
    • in Others https://www.jiqizhixin.com/articles/071301
  • Team Name： SDU-Legend As a Team Leader
    • SDU is short of Shandong Univ. , Legend just represent the Advisor‘s Jokes about me

Education

• MSc. Computer Architecture
  • 2015.07-2018.06 Shandong University
  • Research: GPGPU Architecture, Cache Coherency, New Non-Volatile Memory，Static Program Analysis
  • Advisor : Lei Ju
    
• BSc. Computer Science and Technology
  • 2011.09-2015.06 University of JiNan

Skills

• Programming
  • C/C++/CUDA
  • Python/Shell
• Writing
  • latex/markdown
• Language
  • Chinese/English

Publications

• Shared last-level cache management for GPGPUs with hybrid main memory. In 2017 Design,Automation and Test in Europe Conference and Exhibition (DATE) (pp. 25-30).IEEE. (best paper nomination)
• Shared Last-level Cache Management and Memory Scheduling for GPGPUs with Hybrid Main Memory. ACM Trans. Embedd. Comput. Syst. (Volume 17Issue 4, August 2018)
• Compiler Assisted Cache Coherence for GPGPUs. (Master Thesis)

Patents

• https://www.patentguru.com/cn/CN113296837A
• https://www.patentguru.com/cn/CN113360157A