Contact

• Email
  • [email protected]
• Address
  • No. 1122 Xiangwang Street, Yuhang District, Hangzhou

Education

• MSc. Software Engineering
  • 2015.07-2018.06 Shandong University
    
  • Research: GPGPU Architecture, Cache Coherency,New Non-Volatile Memory
    
• BSc. Computer Science and Technology
  • 2011.09-2015.06 University of JiNan

Project @ Alibaba 2018.07-Now

• Coordinate software and hardware Optimization for DNN Accelerator implemented by FPGA
  • 2018.07-2019.12
  • Graph Optimization/ Pipeline Optimization
• Coordinate software and hardware Optimization for CNN Accelerator implemented by FPGA
  • 2019.06-2019.10
  • Register Allocation /IR Optimization/Code Generation
• Wasm Compiler ：Accelerate Ant block chain smart contract in T-Head C910
  • 2019.12-2020.04

Project @ SDU-Embedded 2015.07-2018.06

• Shared Last Level Cache management and Memory Scheduling for GPGPU with hybrid Main Memory
  • 2016.1-2016.12
  • publish 2 papers to DATE 2017 and TECS 2018 with Ph.D Guan Wang
• Compiler Assisted Cache Coherence for GPGPUs
  • 2017.01-2018.03
  • submit to DAC 2019 ,weak Rejected；Master Thesis
  • submit to DAC 2020
• Energy Efficient Object Detection for Edge Computing
  • 2017.12-2018.05
  • 3rd place in DAC SDC 2018 GPU group
  • News in SDU. https://www.view.sdu.edu.cn/info/1023/106392.htm
  • Team Name： SDU-Legend； As a Team Leader
  • SDU is short of Shandong Univ. , Legend just represent the Advisor‘s Jokes about me

Skill

• Programming
  • C/C++/CUDA
  • Python/Shell
• Writing
  • latex/markdown
• Language
  • Chinese/English

Publication

• Shared last-level cache management for GPGPUs with hybrid main memory. In 2017 Design,Automation and Test in Europe Conference and Exhibition (DATE) (pp. 25-30).IEEE. (best paper nomination)
• Shared Last-level Cache Management and Memory Scheduling for GPGPUs with Hybrid Main Memory. ACM Trans. Embedd. Comput. Syst. (Volume 17Issue 4, August 2018)
• Compiler Assisted Cache Coherence for GPGPUs. (Master Thesis)