Curriculum Vitae

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Education

  • MSc. Software Engineering
    • 2015.07-2018.06 Shandong University
    • Research: GPGPU Architecture, Cache Coherency,New Non-Volatile Memory
    • Advisor : Lei Ju
  • BSc. Computer Science and Technology
    • 2011.09-2015.06 University of JiNan

@ ByteDance 2020.07-Now

  • TVM Graph Optimization for NLP Model
  • ByteDance Complier Toolchains
  • ARM Server Complier Optimization

@ Alibaba 2018.07-2020.07

  • Coordinate software and hardware Optimization for DNN Accelerator implemented in FPGA
    • Graph Optimization/ Pipeline Optimization
  • Coordinate software and hardware Optimization for CNN Accelerator implemented in FPGA
    • Register Allocation /IR Optimization/Code Generation
  • Wasm Compiler ：Accelerate Ant block chain smart contract in T-Head C910
    • front end , wasm to llvm IR
  • ARM Compiler Toolchains Support
    • build benchmark system for Compiler optimization
    • general optimization like pgo/lto/autofdo

@ SDU-Embedded 2015.07-2018.06

  • Shared Last Level Cache management and Memory Scheduling for GPGPU with hybrid Main Memory
    • 2016.1-2016.12
    • Main idea : memory coalescing aware cache management
    • NVM vs DRAM trade off : energy efficient main memory scheduling
    • publish 2 papers to DATE 2017 and TECS 2018 with Ph.D Guan Wang
  • Compiler Assisted Cache Coherence for GPGPUs
    • 2017.01-2018.03
    • a static analysis framework for thread block and cache block index
    • software strategy to eliminate cache coherence
  • Energy Efficient Object Detection for Edge Computing

Skills

  • Programming
    • C/C++/CUDA
    • Python/Shell
  • Writing
    • latex/markdown
  • Language
    • Chinese/English

Publications